Throughout the prior art, metal gate integration has proven difficult to achieve in a conventional process flow for MOS transistors. Most metal gate materials interact with the gate dielectric during the high temperature processing needed for source/drain (S/D) junction activation anneals. The need to keep the metal gate stack from receiving high temperature anneals has lead to the development of the “gate last” or “replacement gate” process for which the gate stack is fabricated last and remains below 500° C. during subsequent processing. Although the prior art replacement gate process increases the number of material choices for a metal gate, the process complexity and cost increases.
It is known in the prior art to form self-aligned silicided metal gates by reacting polycrystalline silicon with a metal. For example the prior art process begins with providing a precursor structure that includes a semiconductor substrate having one or more patterned gate regions separated from each other by one or more isolation regions, each gate region containing at least a gate dielectric and a polysilicon gate conductor. Dielectric cap and spacer structures can be respectively formed on top of and along sidewalls of each gate region as well. Subsequently, source/drain implants are performed to form source and drain regions, during which the polysilicon gate conductor is protected by the dielectric cap and spacer. Next, the dielectric cap is non-selectively removed from the top of each gate region, and then a silicide metal, such as Ni or Co, is deposited on the entire structure. An optional oxygen diffusion barrier layer can be formed atop the silicide metal, and then annealing is performed to cause reaction between the polysilicon and the silicide metal in both the gate region and the source and drain regions. Depending on the metal, a low resistivity metal silicide can be formed by utilizing a single annealing step. After the single anneal, any unreacted metal and the optional oxygen diffusion barrier is removed, and if needed, a second annealing step may be performed to form a low resistivity metal silicide. In such a manner, the salicidation process described above simultaneously forms a fully silicided metal gate and metal silicide surface layers in the source/drain regions.
This prior art process does not allow independent salicidation of the gate region and the source/drain regions, and it can only form metal silicide gates and source/drain surface metal silicide layers of approximately the same thickness, i.e., about 100 nm. However, the gate region and the source/drain regions typically have significantly different silicide requirements. Specifically, the source/drain surface metal silicide layers should be relatively thin (e.g., about 20 nm) to prevent source/drain punchthrough, while the metal silicide gate is typically much thicker.
Therefore, the thick source/drain surface metal silicide layers formed by the above described prior art process can be problematic for a few reasons. First, the silicide can extend underneath the gate region, thereby shorting the device. Secondly, the thick source/drain metal silicide can also be problematic given the recess of the isolation regions of the device caused by the non-selective removal of the dielectric cap from the gate region. Specifically, the silicide in the prior art process can short across devices separated by narrow isolation regions. Thirdly, the thick silicide may consume the silicon in the extension regions under the spacers leading to poor device performance.
Hence, there is a continuing need for improved methods that produce a thick and fully silicided metal gate and a much thinner source/drain silicide.